In reply to rshrig:
The syntax found in 1800 defines what is legal. Specificaly,
clocking_item ::=
default default_skew ;
| clocking_direction list_of_clocking_decl_assign ;
| { attribute_instance } assertion_item_declaration
assertion_item_declaration ::=
property_declaration
| sequence_declaration
| let_declaration
// Note that declarations are NOT assertion statements that include:
concurrent_assertion_statement ::=
assert_property_statement
| assume_property_statement
| cover_property_statement
| cover_sequence_statement
| restrict_property_statement
Ben Cohen
http://www.systemverilog.us/
For training, consulting, services: contact
http://cvcblr.com/home
*
SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
* A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
* Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
*
Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
* Component Design by Example ", 2001 ISBN 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
--------------------------------------------------------------------------
1)
https://verificationacademy.com/forums/systemverilog/vf-horizonspaper-sva-alternative-complex-assertions
2)
http://systemverilog.us/vf/SolvingComplexUsersAssertions.pdf
3) "Using SVA for scoreboarding and TB designs"
http://systemverilog.us/papers/sva4scoreboarding.pdf
4) "Assertions Instead of FSMs/logic for Scoreboarding and Verification"
https://verificationacademy.com/verification-horizons/october-2013-volume-9-issue-3
5) SVA in a UVM Class-based Environment
https://verificationacademy.com/verification-horizons/february-2013-volume-9-issue-1/SVA-in-a-UVM-Class-based-Environment
