Assertion - if and only if

SystemVerilog
,
1

hi all,
I am trying to write an assertion where the result should occur “if and only if” the condition happens.
the obvious way would be to write 2 assertions:

  1. condition |-> result
  2. if result |-> condition

my question is , is there a smarter way to do this?

thanks

2

In reply to gidon:

You can do

property_expr1 iff property_expr2

although getting the timing of the properties to sync may be a challenge.

3

In reply to dave_59:

thanks Dave.
I will try this.