Assertion failure at every clk

SystemVerilog
, ,
1

I have written assertion

property state_chnge;
 @(posedge clk)
  (reset1 && reset2) && 
  (state==2'h0)|=> (state==2'h2);
endproperty
Assert_chnage : assert property(state_change);

I am writing this assertion to check when reset1 and reset2 are high
State moves from 2’h0 to 2’h2. But after I run it, it shows failed at every Clk tick even when it is in state 2’h2. that is it shows assertion failed even if antecedent fails. I don’t understand this part.
Is there a way to write this in such a way that. Assertion should not be shown as failed if antecedent fails.
Please correct me if I am wrong somewhere.

2

In reply to Satputesb:

Your assertions works for me. It would really help to show a complete example, like below. This produces a single pass and single fail.

module top;
  bit clk=1,reset1=1,reset2=1;
  logic [1:0] state;

  always #5 clk=!clk;
  
  initial begin
    @(posedge clk) state = 1;
    @(posedge clk) state = 2;
    @(posedge clk) state = 0; 
    @(posedge clk) state = 2; // pass
    @(posedge clk) state = 2;
    @(posedge clk) state = 0;
    @(posedge clk) state = 0; // fail
    @(posedge clk) state = 2;
    @(posedge clk) state = 1;
    $finish;
  end
  
  property state_change;
    @(posedge clk)
    (reset1 && reset2) &&  (state==2'h0)|=> (state==2'h2);
  endproperty
  Assert_change : assert property(state_change) $info("pass"); else $error("fail");
endmodule