In reply to UVM_LOVE:
The application if your test vectors because you are very much dependent on the sequence in which the simulator processes the code. You have:
If a=1 is processed by the simulator BEFORE the (@(posedge clk) a |-> …
the sampled value of “a” is 1. HOWEVER,
If a=1 is processed by the simulator AFTER the (@(posedge clk) a |-> …
the sampled value of “a” is 0, the defaulted value in the declaration.
SVG has explicit timing regions to prevent this issue. See my answer at https://verificationacademy.com/forums/systemverilog/understanding-systemverilog-scheduling-better
The key here is that your test vectors should be applied with a nonblocking assignment (i.e., the <= ). This is the template I use to check assertions. I modify the variables and constraints as needed.
module top;
timeunit 1ns; timeprecision 100ps;
`include "uvm_macros.svh"
import uvm_pkg::*;
bit clk, a, b, reset_n;
default clocking @(posedge clk); endclocking
initial forever #10 clk = !clk;
initial begin
$timeformat(-9, 0, " ns", 10);
$display("%t", $realtime);
end
always @(posedge clk) begin
end
property p;
int v;
@(posedge clk) disable iff (reset_n == 0) a |-> b;
endproperty
initial begin
bit v_a, v_b, v_err;
repeat (200) begin
@(posedge clk);
if (!randomize(
v_a, v_b, v_err
) with {
v_a dist {
1'b1 := 1,
1'b0 := 1
};
v_b dist {
1'b1 := 1,
1'b0 := 2
};
v_err dist {
1'b1 := 1,
1'b0 := 15
};
})
`uvm_error("MYERR", "This is a randomize error");
a <= v_a;
if (v_err == 0) b <= v_b;
else b <= !v_b;
end
$finish;
end
endmodule
Thank you Ben. (I’m new for SVA)
Actually I’m confused that assertion result will be depended by the EDA simulator and to prevent issue assertions Test vectors have to be used in Non-Blocking( =>).
In reply to UVM_LOVE:
The tools are OK. SV has specific zones when in a time step different types of activities are processed. This is needed because a simulator tool computes sequentially but must emulate concurrency. The style used in that link can lead to errors depending on how a tool handles the model, and this is not a violation of 1800. There is nothing in 1800 that specifies in which sequence the following code is handled:
Test vector can build-up in Blocking assignment. but assertion result depends on Tool
such as something Tool will work
If a=1 is processed by the simulator BEFORE the (@(posedge clk) a |-> …
the sampled value of “a” is 1. HOWEVER,
If a=1 is processed by the simulator AFTER the (@(posedge clk) a |-> …
the sampled value of “a” is 0, the defaulted value in the declaration.
To prevent assertion result issue depends on the Tool, you recommend that Non-Blocking assignment would use in Test vector.
SVG requires proper coding style, regardless of the tools.
Bad coding style may yield unpredictable results depending upon how tools computes the model per 1800 rules; meaning GIGO. Bad style |-> unpredictable results
1800 provided the right syntax and guidelines to emulate cncurrency.
Test vector can build-up in Blocking assignment.
NO. You need to use nonblocking assignment or clocking blocks (see 1800)
but assertion result depends on Tool such as something Tool will work
I didn’t say that. The scheduling of the model is well defined. My figure in that paper is a graphical view of what and where things are processed.
If a=1 is processed by the simulator BEFORE the (@(posedge clk) a |-> …
the sampled value of “a” is 1. HOWEVER,
If a=1 is processed by the simulator AFTER the (@(posedge clk) a |-> …
the sampled value of “a” is 0, the defaulted value in the declaration.
I was providing an example of the issue if coding styles are incorrectly used.
To prevent assertion result issue depends on the Tool, you recommend that Non-Blocking assignment would use in Test vector.
The commendation is a language recommendation, not a tool problem.
Example: You put your car in NEUTRAL gear, press the gas pedal, and then complain that the car is not moving forward. You wonder why, and then you blame the car.
SYstemVerilog is a nice flexible language, but if used incorrectly can yield unpredictable results. blocking assignments occur when they are seen, nonblocking assignement are queued and then processed in the nonbloking region.
Ben