Assertion Error

SystemVerilog
,
1

Hi,

Trying to learn assertions here. I am trying to write an assertion to check- when ‘rst’ goes low, ‘out’ too goes low.
The waveform shows this is happening correctly. But still my assertion fails. Can anyone point where I am going wrong.

Here is my DUT-

module simpleadder (simpleadder_if dif);
 //import uvm_pkg::*;
  always @(posedge dif.sig_clock or dif.sig_rst == 1'b0) begin	// active low rst
	if (dif.sig_rst==1'b0) 
		begin
		dif.sig_out <=  0;
        	dif.sig_en_o <= #1 0;
		end

and the assertion that I wrote-

`include “bind_assertions.sv”

module adder_assertions(input logic clk,
			input logic rst,
			input logic [`LENGTH:0]out
	       	);
	
	//always@(posedge clk or rst == 1'b0)
	always @(negedge rst)
	begin	
		 assert (out == 0) $display("running assertions");
		else
		begin 
			$error(" out should be zero at reset ");
			$display ("out=%0d expected 0", out);
		end
	end
	
	endmodule

The Error-

UVM_INFO small_seq.sv(17) @ 0: uvm_test_top.sa_env.sa_agent.sa_seqr@@sml_seq [SMALL SEQ] body called

UVM_INFO testbench.sv(29) @ 2000: reporter [id1] Reset applied

** Error: out should be zero at reset

Time: 20 ns Scope: simpleadder_tb_top.dut.adder_assertions_inst File: F:/STUFF/Adder/assertions/assertions.sv Line: 14

out=9 expected 0

UVM_INFO testbench.sv(31) @ 4000: reporter [id1] Reset released

Thanks,
Swastika

2

In reply to Swasti101:

Try:

 

  a_out_0_at_rst : assert property (@(posedge clk) 
    $fell(rst) |=> out == 0)) 
  else `uvm_error ("a_out_0_at_rst", 
         $sformatf("out is not 0 after RST, its value is: 0x%0x", $sampled(out))

I used concurrent assertion style to make it easier.

Regards
Srini
http://verifnews.org/jdi/

3

In reply to Srini @ CVCblr.com:

Thanks Srini @ CVCblr.com. That worked.
Can you please help me understand what was wrong in my code ?

Regards,
Swastika

4

In reply to Swasti101:

Because you used an immediate assertion, ant the point in time when it executed, out has not been updated.