Assertion to ensure i do not see a grant before a req asserts?

[saikalyankrishna]

Hi,

How do i ensure a grant does not assert before a req asserts in a design via an assertion ?

[ben2]

In reply to sai kalyan krishna:

See my last reply at
https://verificationacademy.com/forums/systemverilog/sva-need-help-writing-assertion-requirement

[saikalyankrishna]

In reply to ben@SystemVerilog.us:

Thanks Ben !