In reply to email@example.com:
Keep in mind that an assertion is a statement or directive that a given property is required to hold. Assertions can be expressed in many ways, including regular code.
In SystemVerilog, that can be done in SVA or other plain SystemVerilog options.
Your requirement to verify that a wave of any shape, the duration of highs and lows of s1 are the same as s2, but delayed.
It's too complex to do in SVA, but you can use the task method, as explained in my paper
SVA Alternative for Complex Assertions
Below is an untested method where I measure that the duration in cycles of s1 pulse in high level is the same as s2 (delayed) also staying a 1 for that duration.
You need to do the same for when the signals are in the low state, the t_fell() task.
task automatic t_rise();
int s1_r1r1; // S1 rise to rise
int s2_r1r1; // S2 rise to rise
begin // record wave for s1
while (s1==1) begin
s1_r1r1++; // compute #cycles s1==1
while (s2==1) @(posedge clk); // wait for s2 to rise
while (s2==1) begin
s2_r1r1++; // compute #cycles s1==1
label: assert (s1_r1r1==s2_r1r1)
else $error("s1 high pulse != s2 high pulse ");
always @(posedge clk) begin
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* SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
* A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
* Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
* Component Design by Example ", 2001 ISBN 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
1) SVA Alternative for Complex Assertions
3) SVA in a UVM Class-based Environment