I am trying to add a connectivity assertion here
DUT:
module dut ();
wire v_connect;
vibb vbbb (
.vbt (v_connect)
)
viba vbba (
.vbt (v_connect)
)
vibc vbbc (
.vbt (v_connect)
)
endmodule
Basically it goes to each block and vbt is a power signal defined by wreal vbt.
I have added assertion something like this :
module assertion ()
property p_v_conn_check;
@( posedge msvtb.clk_sys)
disable iff ((!mtb.DUT.rst))
(1'b1 |-> mtb.DUT.v_connect == mtb.DUT.vbba.vbt );
endproperty
a_vbt_conn_check : assert property(p_v_conn_check)
else $fwrite( FOUT, "ASSERT FAIL :);
endmodule
When i do this the wire declared in DUT v_connect goes to Z.
Is there any better way to add conn checks all the blocks here
Thanks in advance !!
In reply to tejasakulu:
It is highly unusual to use assertions for connectivity; I never used it in that mode.
The goals of assertions is to specify and verify requirements.
You’re putting unnecessary loads on the simulation tool, particularly if you have a lot of connections.
There are tools that take a hierarchical design and graphically display the architecture (connections between modules and also within a module, though that can be complex).
If you insist on using assertions, I would eliminate the implication operator.
Thus,
I would also limit the number of cycles I enable these assertions.
You do not need the whole extensive run here.
Would a detailed code review do the job instead of very meaningless assertions?