I have clk, in, out signals. I have 2 conditions.
a) out is asserted immediately if in=1.
b) out is -de-asserted after n cycles if in=0;
I tried writing below code, but its not working as expected
`define TRUE 1'b1
if(in) `TRUE |-> out
else `TRUE |=> ##[1:5] out;
Please suggest me whether it is the write way to do it. If there is any better way please suggest