Assertion completion time

SystemVerilog
1

could you please let me know whether the assertion fails if valid is not changing from 1 to 0. if it is not failing how to make sure whether it fails.


property minimumOnePluse(logic resetb,logic valid);
 $rose(resetb) |->##[1:$] $rose(valid) ##1 valid[*1:$] ##1 $fall(valid);

endproperty 

assert property (@ (posedge  ipclk) minimumOnePluse(resetb[0:0],valid[0:0]));
2

[i]In reply to srbeeram:[/i
Use the strong in the consequent.
After the $finish, if the assertion does not complete, it will fail.
For style, consider using the goto operator.
Ben Ben@systemverilog.us

3

In reply to ben@SystemVerilog.us:

Thanks ben for the clarification.could you please let me know how to write with goto operator.

4

In reply to srbeeram:

Study the goto operator or do a search. I talked about it on this for.
Books and 1800 cover it.
Ben Ben@systemverilog.us