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Assertion to compare data values

SystemVerilog 4646
assertion 86
syed taahir ahmed
syed taahir ahmed
Full Access
101 posts
October 03, 2019 at 10:53 am

Hi,

There is scenario.
1) for every ready Singal which is high until valid Singal gets triggered. And the ready goes low the next cycle along with valid.
2) for every ready & valid, there is data value which should not be equal to previous data value, this keeps repeating for many times.

How do I make sure that first data and consecutive data are unique

Thanks

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Solution

Solution

ben@SystemVerilog.us
ben@SystemVerilog.us
Full Access
1781 posts
October 03, 2019 at 1:49 pm

In reply to syed taahir ahmed:

Check out my replies that address how supporting logic can solve this uniqueness issue.
https://verificationacademy.com/forums/systemverilog/need-help-write-assertion
https://verificationacademy.com/forums/systemverilog/assertion-expected-data-check/review-users-question
https://verificationacademy.com/forums/systemverilog/counting-number-events-clock-while-clock-o-forbidden

Ben Cohen
http://www.systemverilog.us/
For training, consulting, services: contact http://cvcblr.com/home
* SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
* A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
* Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
* Component Design by Example ", 2001 ISBN 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
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1) SVA Alternative for Complex Assertions
https://verificationacademy.com/news/verification-horizons-march-2018-issue
2) https://verificationacademy.com/forums/systemverilog/sva-package-dynamic-and-range-delays-and-repeats
3) SVA in a UVM Class-based Environment
https://verificationacademy.com/verification-horizons/february-2013-volume-9-issue-1/SVA-in-a-UVM-Class-based-Environment

syed taahir ahmed
syed taahir ahmed
Full Access
101 posts
October 03, 2019 at 2:31 pm

In reply to ben@SystemVerilog.us:

Thanks Ben, I will work on my issue with your pointers

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