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  • Assertion : ClkGate state and TransactionCount assertion

Assertion : ClkGate state and TransactionCount assertion

SystemVerilog 6304
#assertion 34
naaj_ila
naaj_ila
Full Access
28 posts
November 28, 2022 at 1:22 am

FSMstate goes to Clkgate state and clk will be gated when TransCnt=0 after some 0-10 clock cycle
FSM state ungates the clk when TransCnt!=0 after some 0-10 clk cycles
ClkGateState=2
Idle=0
I need to write some assertions for that
1. 

//Check when TransCnt=0, Clock will be Gated till TransCnt!=0
   property assert1(bit reset);
   @(negedge TBclk) disable iff(!reset) 
   (TranCnt==0) |-> ##[0:10] (Clk == 0) throughout (~(TransCnt==0)[->1])); 
 endproperty
  Worked for me
 
2. //Check when State=Gatedstate, TransCnt=0
   property assert2(bit reset);
   @(negedge TBclk) disable iff(!reset) 
   (State==2)[*10] |-> (TransCnt==0) 
 endproperty
 
 
   This is not working , 
   Once TransCnt=0, after some 10 clock cycles, State =2. From here Assertion triggers and Passes.
   When TransCnt=1, after some 10 clock cycles State will be zero. -> ASSERTION FAILS HERE as State is takign some 10 clks to go to IDLE.
 

Can someone help me to work on 2nd assertion
So Assertion is failing at

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ben@SystemVerilog.us
ben@SystemVerilog.us
Full Access
2594 posts
November 28, 2022 at 11:16 am

In reply to naaj_ila:
I don't understand the issue.
Maybe you need a $rose(State==2)

naaj_ila
naaj_ila
Full Access
28 posts
November 28, 2022 at 7:18 pm

In reply to ben@SystemVerilog.us:

I want to write an assertion similarly like this
1.When Clk is Gated(state=2) , i want to make sure TransCnt=0.
Note:: when TransCnt!=0, Clk will be Ungated within 0 to 10 clkcycles.

 property clkgate_state_p(bit reset);
   @(negedge TBCLK) disable iff(!reset) 
   (State_ps == 2)  |-> $past((TransCnt==0),[0:10]);  
 endproperty

I want to make sure TransCnt=0 when State=2. TransCnt will be zero before some 0-10 clk cycles.
Similarly like above assertion

ben@SystemVerilog.us
ben@SystemVerilog.us
Full Access
2594 posts
November 28, 2022 at 8:32 pm

In reply to naaj_ila:

// $past(rnge) is illegal Illegal 
 (State_ps == 2)  |-> $past((TransCnt==0),[0:10]);  
 
// However, you can use the endpoints (.triggered) of a sequence. Thus, 
// UPDATED SOLUTION IN MY LAST POST BELOW

Ben Cohen
http://www.systemverilog.us/
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
...
1) SVA Package: Dynamic and range delays and repeats https://rb.gy/a89jlh
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3) Papers:
Understanding the SVA Engine,
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Reflections on Users’ Experiences with SVA, part 1
https://verificationacademy.com/verification-horizons/march-2022-volume-18-issue-1/reflections-on-users-experiences-with-systemverilog-assertions-sva
Reflections on Users’ Experiences with SVA, part 2
https://verificationacademy.com/verification-horizons/july-2022-volume-18-issue-2/reflections-on-users-experiences-with-sva-part-2
SUPPORT LOGIC AND THE ALWAYS PROPERTY
http://systemverilog.us/vf/support_logic_always.pdf
SVA Alternative for Complex Assertions
https://verificationacademy.com/news/verification-horizons-march-2018-issue
SVA in a UVM Class-based Environment
https://verificationacademy.com/verification-horizons/february-2013-volume-9-issue-1/SVA-in-a-UVM-Class-based-Environment
SVA for statistical analysis of a weighted work-conserving prioritized round-robin arbiter.
https://verificationacademy.com/forums/coverage/sva-statistical-analysis-weighted-work-conserving-prioritized-round-robin-arbiter.
Udemy courses by Srinivasan Venkataramanan (http://cvcblr.com/home.html)
https://www.udemy.com/course/sva-basic/
https://www.udemy.com/course/sv-pre-uvm/
naaj_ila
naaj_ila
Full Access
28 posts
November 28, 2022 at 9:36 pm

In reply to ben@SystemVerilog.us:

Hi
This code looks like after State went to Gate, then check TransCnt after some 0-10 clk cycles,
Actually i need to check the past values of TransCnt should be zero within 10 clk cycles.(Kind of reverse Check)

sequence s; ##[0:10] TransCnt; endsequence
property clkgate_state_p(bit reset);
  @(negedge TBCLK) disable iff(!reset) 
  (State_ps == 2)  |-> s.triggered;  
endproperty

Solution

Solution

ben@SystemVerilog.us
ben@SystemVerilog.us
Full Access
2594 posts
November 28, 2022 at 10:03 pm

In reply to naaj_ila:

You correct, I misapplied the use of endpoint.
In the past I used with the reapeat, like a[*10]

sequence s; a ##[1:2] 1; endsequence
b |-> a;
 
attempt       1   2   3   4   5   6   7   8
a             0   1   0   1   0   0   1   9
s.triggered           1   1               1    1 // 2nd and 7th attempt
s.triggered                   1   1              // 4th attempt
b                     1           1

sequence s; TransCnt ##[0:10] 1; endsequence
property clkgate_state_p(bit reset);
  @(negedge TBCLK) disable iff(!reset) 
  (State_ps == 2)  |-> s.triggered;  
endproperty

Apologies. Thanks for pointing this out.
Ben
naaj_ila
naaj_ila
Full Access
28 posts
November 28, 2022 at 10:32 pm

In reply to ben@SystemVerilog.us:

Thanks a lot ben, It worked.
Actually there is big combination of code , i asked a small example.
I implemented in my code and it worked.

I understood very clearly how it is working.

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