Assertion to check without using any clock, if signal A is high signal B must be high

SystemVerilog
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I want to write a simple assertion where if signal A is high , signal B must be high else generate error. If A is low, no check is needed.
I dont want to use clock as then my check will be limited to the clock period and any glitch smaller than clock period could be missed.
Thanks in advance for suggestions.

2

In reply to shals:

immediate assertion + “disable iff !A” can help you solve

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In reply to shals:

If you truly mean “for all time”

assert final (A->B);
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In reply to kangrh007:

Thanks. That helped.