Hi ,
I have a requirement that active-low reset signal can be asserted ( $fell( rst_n ) ) asynchronously but deassertion must be synchronous after the rising edge of clock
Generally I post a code snippet of what I have tried but for the synchronous deassertion part , I am not sure where to even start
Any suggestions ?
Thanks in advance
In reply to Have_A_Doubt:
I am assuming that at the fell of rst_n the clk is running.
I am also assuming that by synchronous, you mean within acceptable bounds of a period.
IN this assertion, I save at the posedge of rst_n the current time.
I then wait till the next clock and measure the time difference to be within limits.
module m;
bit clk, rst_n;
let period=10;
property p;
realtime v;
@(posedge rst_n) (1, v=$realtime) ##0
@(posedge clk) ($realtime-v < period+1) && // <11
($realtime-v > period-1); // > 9
endproperty
ap_p: assert property(@(posedge clk) p);
endmodule
// may need to adjust the units
$realtime-v < period*1ns +0.1ns) && // <10.1ns
($realtime-v > period *1ns-0.1ns)
====================
Reflections on Users’ Experiences with SVA,
Reflections on Users’ Experiences with SVA, part 2
SUPPORT LOGIC AND THE ALWAYS PROPERTY
SVA Alternative for Complex Assertions
https://verificationacademy.com/news/verification-horizons-march-2018-issue
SVA in a UVM Class-based Environment
https://verificationacademy.com/verification-horizons/february-2013-volume-9-issue-1/SVA-in-a-UVM-Class-based-Environment
SVA for statistical analysis of a weighted work-conserving prioritized round-robin arbiter.
https://verificationacademy.com/forums/coverage/sva-statistical-analysis-weighted-work-conserving-prioritized-round-robin-arbiter.
—---------------
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
…
SUPPORT LOGIC AND THE ALWAYS PROPERTY
http://systemverilog.us/vf/support_logic_always.pdf
SVA Alternative for Complex Assertions
https://verificationacademy.com/news/verification-horizons-march-2018-issue
SVA in a UVM Class-based Environment
https://verificationacademy.com/verification-horizons/february-2013-volume-9-issue-1/SVA-in-a-UVM-Class-based-Environment
SVA for statistical analysis of a weighted work-conserving prioritized round-robin arbiter.
https://verificationacademy.com/forums/coverage/sva-statistical-analysis-weighted-work-conserving-prioritized-round-robin-arbiter.
Udemy courses by Srinivasan Venkataramanan (http://cvcblr.com/home.html)
https://www.udemy.com/course/sva-basic/
https://www.udemy.com/course/sv-pre-uvm/
In reply to ben@SystemVerilog.us:
I am assuming that at the fell of rst_n the clk is running.
Yes , the clk would be running throughout .
I am also assuming that by synchronous, you mean within acceptable bounds of a period.
This part I was confused about .
The requirement ( from AXI Spec ) was simply mentioned as “but deassertion must be synchronous after the rising edge of clock”
Ben have 2 follow-up questions ::
(1) The clocking - event written in assert property can be removed right ?
as @(posedge rst_n) in antecedent would override @(posedge clk) in assert property
(2) What if I were to write it as ::
property p;
realtime v;
@(posedge clk) (1, v=$realtime) // @( posedge clk ) written First
##0 @(posedge rst_n) ($realtime - v) inside { [ min : max ] } ;
endproperty
ap_p: assert property( p );
In reply to Have_A_Doubt:
The requirement ( from AXI Spec ) was simply mentioned as “but deassertion must be synchronous after the rising edge of clock”
Typically, resets come off of an RC circuit that holds that signal low until the RC time.
For the signal to be synchronous on the positive edge of clk, there is a need for special logic, unless you want to pass that RC output directly into a flop and make the flow the main reset line.
FIrst the 1st case, that rst_n can be implemented with something like:
wire rst_rc_n; // reset off of an RC (resistor/capacitor) circuit with a long time constant
bit rst_n; // the reset for the design
bit rst_ff, clk; //
always @(posedge clk) rst_ff <= rst_rc_n; // may need to reset the FF or assume RC is long enough
assign rst_n=(rst_rc_n && !rst_ff) || rst_ff
The clocking - event written in assert property can be removed right ?
YES
On the your question on the inside,
module m;
realtime v= 10.0;
let min=9.9;
let max=10.1;
initial begin
if(v inside{[min:max]}) $display("PASS");
else $display("FAIL");
end
endmodule // simulation result:
# PASS
// *********
// Thus, your code looks OK
let min=9.1;
let max=10.1;
property p;
realtime v;
// Run a test model.
@(posedge clk) (1, v=$realtime) // @( posedge clk ) written First
##0 @(posedge rst_n) ($realtime - v) inside { [ min : max ] } ;
// 1800:16.6 Boolean expressions has example of using realtime
endproperty
ap_p: assert property( p );