Assertion to check speed mode in i2c

Hello,

I want to check positive level of clock at every clock cycle until stop condition.

So,in i2c suppose the positive level of scl(serial clock) is 4000ns, i want to check and compare this time unit until my stop condition is detected,
i tried until,until_with and throughout but it is not working for me.

Looking for your positive acknowledgement.

Consider writing your verification model using tasks.
See SVA Alternative for Complex Assertions
Verification Horizons - March 2018 Issue | Verification Academy

Consider using fork join_any and flags.
For example (not your issue, but an example of the methodology). However do read my paper as it addresses more on the methodology,

 
// b==0  as long as "a==1" 
always @(posedge a) begin
  bit ahappen;
  assert (! b);
  fork
     @(posedge b) ahappen=1'b1;
     @(negedge a) ;
  join_any
  assert (ahappen=1'b0);
end

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr

  • SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
  • A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
  • Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
  • Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
  • Component Design by Example ", 2001 ISBN 0-9705394-0-1
  • VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
  • VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115

  1. SVA Alternative for Complex Assertions
    Verification Horizons - March 2018 Issue | Verification Academy
  2. SVA: Package for dynamic and range delays and repeats | Verification Academy
  3. SVA in a UVM Class-based Environment
    SVA in a UVM Class-based Environment | Verification Horizons | Verification Academy