Assertion to check setup and hold window of signal

Hi All,

I have a clock and serial data signal. i would like to check serial data signal whether it is stable or not in setup and hold window with respect to clock.

Kindly help me ASAP.

Regards,
Siva

Forums: SystemVerilog | Verification Academy.
Updaded link
Ben SystemVerilog.us

In reply to ben@SystemVerilog.us:

Ben, I am not able to open the link which is shared by you…

In reply to sivakrishna:

I updated the link, try it again. There is a “.” At the end. Otherwise do a google search on
Ben Cohen setup hold

I tried the link above, and it works for me

Forums: SystemVerilog | Verification Academy.