Assertion to check real value

SystemVerilog
,
1

Hi All,
I am having 2 questions
1.
real vout1;
at reset vout1 ='z;
how to check that in assertion ?
$isunknown(vout1) is not working.

  1. how to limit the assertion to check upto x decimal. (x =1,2,3,4)
    example real vout2 = 3.2100002345;

thanks

2

In reply to Abhisek11:
You’ll need to do type conversions.
See system verilog - The best way to convert a real valued number to an integer value larger than 32 bits? - Stack Overflow

 
module m;
  real vout1 = 'Z, test_;
  real vout2 = 3.2100002345;
  real test_value;
  typedef logic [41:0] uint42_t;
  uint42_t v42;
  //A implicit cast from real to integral gives you what you want with rounding
  initial begin
    test_value = 2.0 ** 39.5;
    // Or you can use an explicit cast
    // typedef logic [41:0] uint42_t;
    test_value = uint42_t'(2.0 ** 39.5);
    vout2 = 3.2100002345;
    v42 = uint42_t'(vout2);
    v42 = uint42_t'(vout1);
    am_vout1 : assert ($isunknown(v42)); // line 17
    // Simulation 
    //  Error: Assertion error.
    //    Time: 0 ns  Scope: m.am_vout1 File: C:/ben_play/./real2int.sv Line: 17
    #10; 
    v42 = v42 | 10'b0000xzzz00;
    am_vout : assert ($isunknown(v42));
  end
endmodule
3

In reply to ben@SystemVerilog.us:

thanks Ben