Assertion to check number of ones is even!

SystemVerilog
, , ,
1

//In this code, the assertion is passing even if the number of ones is odd. I’d be happy if you could help me out.

module test();  
bit clk = 1'b1;
bit [15:0] a;

initial begin
    forever #5 clk = ~clk;
end

property p1;
    @(posedge clk) (($countones(a)%2)==0);
endproperty

assert property(p1)
$display("PASS\t[%0t]a:%b\tones:%d",$time, a, $countones(a));
else 
$display("FAIL\t[%0t]a:%b\tones:%d",$time, a, $countones(a));

always @(posedge clk) begin	
        a = $random;
    end

initial
begin
    #100;
    $finish;
end

endmodule
2

In reply to preetam_kale:

Refer to section 16.9.3 of the LRM which describes how to access the values used during the assertion.


module test();  
  bit clk;
  bit [15:0] a;
 
  initial begin
    clk = 0;
    forever #5 clk = ~clk;
  end
 
  property p1;
   @(posedge clk) (($countones(a)%2)==0);
  endproperty
 
  assert property(p1)
    $display("PASS\t[%0t] a:%b\tones:%d",$time, $sampled(a), $countones($sampled(a)));
  else 
    $display("FAIL\t[%0t] a:%b\tones:%d",$time, $sampled(a), $countones($sampled(a)));
 
  always @(posedge clk) begin	
    a <= $random;
  end
 
  initial begin
    #1000;
    $finish;
  end
 
endmodule
3

In reply to cgales:

Thanks, CGales.
I tried tweaking a little and found that it was due to race condition. So, I changed the posedge for checking to negedge and finally getting the correct output.

Code:
module test();
bit clk = 1’b1;
bit [15:0] a;

initial begin
forever #5 clk = ~clk;
end

property p1;
@(negedge clk) ($countones(a)%2==0);
endproperty

assert property(p1)
$display(“PASS\t[%0t]a:%b\tones:%d”,$time, a, $countones(a));
else
$display(“FAIL\t[%0t]a:%b\tones:%d”,$time, a, $countones(a));

always @(posedge clk) begin
a = $random;
end

initial begin
#100;
$finish;
end

endmodule

Output:
VSIM 1> run -all

PASS [5]a:0000000000000000 ones: 0

PASS [15]a:0011010100100100 ones: 6

FAIL [25]a:0101111010000001 ones: 7

FAIL [35]a:1101011000001001 ones: 7

PASS [45]a:0101011001100011 ones: 8

FAIL [55]a:0111101100001101 ones: 9

PASS [65]a:1001100110001101 ones: 8

PASS [75]a:1000010001100101 ones: 6

FAIL [85]a:0101001000010010 ones: 5

PASS [95]a:1110001100000001 ones: 6

** Note: $finish : ./no_of_even_ones.sv(24)