I was wondering if there is a way to do assertion check on signal which has a delay. But the delay of the signal is not fix for every test. All i need is to check that the signal has a delay before it gets the value from a specific signal.
For example, if A equal to 1, X ns later, B will equal to 1. But X is varies for every test.
In reply to lisa.lalice:
If the delay is in clock cycle, it is relatively simple, see the assertion ap_A2B below.
If the delay is in ns, it is more complicated. There, I used the task method explained in my paper Understanding the SVA Engine (link below), but modified it as needed.
Note that 1800’2017 addresses in 31.9.2 Conditions in negative timing checks the use of the $hold and there might be a way to use this. It’s been a very long time since I used this feature, so I’ll let someone else figure it out.
Basically, the process for my approach involves these steps
always @(posedge clk) begin
if($changed(a))
fork
t_chk_delay(2ns);
join_none
end
fork
begin : d_dly
#d;
doned=1'b1;
end :d_dly
begin : change
wait(b == a_start); // b==a should occur after #d
done_chg=1'b1;
end : change
join_none
wait(doned || done_chg);
a_delay_bforeX: assert(doned && !done_chg) else begin
// done delay before change in b
$display("%t spec delay=%t actual delay=%t",
$realtime, d, $realtime-initiTime);
-> e;
end
#3 a_equal_b_after_dly: assert(done_chg) else begin
// done delay before change in b
$display("%t spec NO CHANGE IN b, delay=%t actual delay=%t",
$realtime, d, $realtime-initiTime);
-> e1;
end
You may need to tune the code as needed, but this is my concept.
/* I was wondering if there is a way to do assertion check on signal which has a delay.
But the delay of the signal is not fix for every test.
All i need is to check that the signal has a delay before it gets the value from a specific signal.
For example, if A equal to 1, X ns later, B will equal to 1. But X is varies for every test. */
module top;
`include "uvm_macros.svh"
import uvm_pkg::*;
import sva_delay_repeat_range_pkg::*;
bit clk, a, b;
int d1=2; // in clock cycles
event e, e1;
// Assuming the delay in in clock cycles as defined in a module variable "d1"
ap_A2B: assert property(@ (posedge clk) $changed(a) |->
q_dynamic_delay(d1) ##0 $changed(b) );
// Delay in ns
task automatic t_chk_delay(realtime d);
bit a_start, doned, done_chg; // done d delay, done change
realtime initiTime;
a_start=a;
initiTime = $realtime;
fork
begin : d_dly
#d;
doned=1'b1;
end :d_dly
begin : change
wait(b == a_start); // b==a should occur after #d
done_chg=1'b1;
end : change
join_none
wait(doned || done_chg);
a_delay_bforeX: assert(doned && !done_chg) else begin
// done delay before change in b
$display("%t spec delay=%t actual delay=%t",
$realtime, d, $realtime-initiTime);
-> e;
end
#3 a_equal_b_after_dly: assert(done_chg) else begin
// done delay before change in b
$display("%t spec NO CHANGE IN b, delay=%t actual delay=%t",
$realtime, d, $realtime-initiTime);
-> e1;
end
endtask: t_chk_delay
always @(posedge clk) begin
if($changed(a))
fork
t_chk_delay(2ns);
join_none
end
initial forever #10 clk = !clk;
initial begin
bit[2:0] v;
bit a1, b1;
repeat (200) begin
@(posedge clk);
if (!randomize(a1, b1, v) with {
a1 dist {1'b1 := 1, 1'b0 := 1};
b1 dist {1'b1 := 1, 1'b0 := 1};
v dist {2:= 1, 1 := 1, 4 := 1};
})
`uvm_error("MYERR", "This is a randomize error");
a = a1;
#v b=b1;
end
$finish;
end
endmodule
// Error messages
31 spec delay= 2 actual delay= 1
# 155 spec NO CHANGE IN b, delay= 2 actual delay= 5
# 170 spec delay= 2 actual delay= 0
# ** Error: Assertion error.
# Time: 170 ns Started: 130 ns Scope: top.ap_A2B File: C:/ben_play/chk_delay.sv Line: 13 Expr: $changed(b)
# Local vars : v = 0
# ** Error: Assertion error.
# Time: 190 ns Started: 150 ns Scope: top.ap_A2B File: C:/ben_play/chk_delay.sv Line: 13 Expr: $changed(b)
# Local vars : v = 0
# 195 spec NO CHANGE IN b, delay= 2 actual delay= 5
# ** Error: Assertion error.
# Time: 210 ns Started: 170 ns Scope: top.ap_A2B File: C:/ben_play/chk_delay.sv Line: 13 Expr: $changed(b)
# Local vars : v = 0
# 290 spec delay= 2 actual delay= 0
# 315 spec NO CHANGE IN b, delay= 2 actual delay= 5
# 330 spec delay= 2 actual delay= 0
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact http://cvcblr.com/home.html
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
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