Assertion based doubt

SystemVerilog
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1

I was watching the youtube video (https://www.youtube.com/watch?v=9O6XK61iaCQ) based on difference between goto and non-consequetive repetition operator based assertion.
I was confused why case is passing in C0 column:

2

In reply to amir_sharfu:
The 2nd attempt of “a” should pass. SHow the code
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