ASSERTION from AXI

SystemVerilog
1

AXI4_ERRM_WSTRB
Write strobes must only be asserted for the correct byte lanes as determined from the:
• Start address.
• Transfer size.
• Beat number.

my doubt is for each strobe lane we must write the assertion or not. how to take the start address.

2

In reply to mada saimanasa:

See. ASSERTION from AXI | Verification Academy