Can you please help me with this interview question?
There was a black box which has 8 pairs of input and a single 8 bit output. Each pair in the input has one single bit valid line, and 8 bit input line. When there is change in the status of any of the valid input bit, corresponding input is sampled to black box and there will be change in output. Write an assertion to check if at least 4 bits of the sampled output is changed during the process.
In reply to n347:
bit[7:0] valid;
byte data[7:0];
default clocking @(posedge clk); endclocking
// For a single input/output pair
ap_valid0: assert property(@ (posedge clk)
$changed(valid[0]) |=> $countones($past(data[0]) ^ data[0])==4 );
// For al 8 pairs
generate for (genvar i=0; i<=7; i++)
begin
ap_valid: assert property(@ (posedge clk)
$changed(valid[i]) |=> $countones($past(data[i]) ^ data[i])==4 );
end
endgenerate
Testbench
import uvm_pkg::*; `include "uvm_macros.svh"
module top;
bit clk;
bit[7:0] valid;
byte data[7:0];
default clocking @(posedge clk); endclocking
initial forever #10 clk=!clk;
ap_valid0: assert property(@ (posedge clk)
$changed(valid[0]) |=> $countones($past(data[0]) ^ data[0])==4 );
generate for (genvar i=0; i<=7; i++)
begin
ap_valid: assert property(@ (posedge clk)
$changed(valid[i]) |=> $countones($past(data[i]) ^ data[i])==4 );
end
endgenerate
initial begin
bit va, vb;
repeat(200) begin
repeat(1) @(posedge clk);
if (!randomize(valid, data)) `uvm_error("MYERR", "This is a randomize error");
end
$stop;
end
endmodule
Ben Cohen
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