Hi , I want to write an assertion based on the following application .
Two signals "signalA" and "signalB" are asynchronous . If there is a valid(posedge) singalA between two posedges of signalB then the FSM should got to "state1" else "state2" . Both signalA and signalB can be sampled on much faster clock lets say "clk".Basically singalA is like a small glitch between two posedges of signalB .
Thanks in advance !!