Hello,
If i want to check the signal must not transit from low to high during whole simulation time than how can i achieve this using “throughout” in SVA.
Thanks in Advance. :)
In reply to Dhanesh_Padia:
Is there any specific requirement to use throughout operator? You can check that the signal is always low during entire simulation. The following pseudo properties might be helpful, though I have not tested them.
module top();
logic a;
bit clk;
always #5 clk = ~clk;
initial begin
a = 0;
#50 a = 0; // make this 1 to get error
end
initial #500 $finish;
property mythroughout();
@(posedge clk)
(!a) throughout (1 ## [0:$] 1);
endproperty
property mysimpleprop();
@(posedge clk)
(!a);
endproperty
mythro: assert property (mythroughout()); // using dummy throughout
myprop: assert property (mysimpleprop()); // without using throughout
endmodule
Here I am checking that at every positive clock edge, the value of signal should be zero. This can be done with a dummy throughout clause added after the real signal check. The assertion is checked throughout simulation since concurrent assertions automatically fires at every posedge. As an alternative, one can force the usage of dummy throughout operator as shown in above code.
So both the the assertions will fail, whenever the signal becomes HIGH.
As a side note, basics of assertions are explained here.