Assertion

SystemVerilog
1

HI help me to write assertion logic,
Write an assertion A high for 5 cycles and B high after 4 non-continuous highs of A and finally both A and B are high?
___|====||======================| A

__________________________|=====| B

Thanks & Regards
Rohith

2

I believe this would work, you basically walk it through

$rose (a) ##1!a ##1 a[=1]##1 a[*3] ##0 b => b ##0 a;

you need to tune this approach
Can a be high for 5 cycles? What is the cycle gap for a to be? Would be better if you ha Go signal

$rose(Go) ##0 a ##1!a ##1 a[=1]##1 a[*3] ##0 b => b ##0 a;

you need to tune this approach
Ben systemverilog.us

3

In reply to ben@SystemVerilog.us:

I believe this would work, you basically walk it through

$rose (a) ##1!a ##1 a[=1]##1 a[*3] ##0 b => b ##0 a;

you need to tune this approach
Can a be high for 5 cycles? What is the cycle gap for a to be? Would be better if you ha Go signal

$rose(Go) ##0 a ##1!a ##1 a[=1]##1 a[*3] ##0 b => b ##0 a;

you need to tune this approach
Ben systemverilog.us

Hi ben,
Thanks for giving reply