Please Explain Inline Assertion with Example.
In reply to Mukund Sojitra:
Please Explain Inline Assertion with Example.
This is a terrific interview question!
Ben
Kindly explain to me.
In reply to Mukund Sojitra:
Inline assertion is not a separate concept. It could mean,
- Inline code: SVA is part of SystemVerilog language construct, and it can me coded inline along with Verilog/SV code.
- Or may be, calling concurrent assertions inline inside procedural block?
In reply to Mukund Sojitra:
Please Explain Inline Assertion with Example.
The key to your question is the word “inline”, meaning within a block, like the initial, always, always_comb, always_ff, final, task, function.
As you may also know, there are two types of assertions: concurrent and immediate, and both can be inserted inline; however, there are specific rules to abide by.
Books/online courses or videos/1800’2012 address this topic with rules and examples.
I suggest that you study assertions through such books, 1800, or information easily available through searches.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr
- SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
Thank you very much Mayur.
Thnak you Ben.