Please Explain Inline Assertion with Example

Please Explain Inline Assertion with Example.

In reply to Mukund Sojitra:

Please Explain Inline Assertion with Example.

This is a terrific interview question!
Ben

Kindly explain to me.

In reply to Mukund Sojitra:

Inline assertion is not a separate concept. It could mean,

  • Inline code: SVA is part of SystemVerilog language construct, and it can me coded inline along with Verilog/SV code.
  • Or may be, calling concurrent assertions inline inside procedural block?

In reply to Mukund Sojitra:

Please Explain Inline Assertion with Example.

The key to your question is the word “inline”, meaning within a block, like the initial, always, always_comb, always_ff, final, task, function.

As you may also know, there are two types of assertions: concurrent and immediate, and both can be inserted inline; however, there are specific rules to abide by.

Books/online courses or videos/1800’2012 address this topic with rules and examples.
I suggest that you study assertions through such books, 1800, or information easily available through searches.

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr


Thank you very much Mayur.

Thnak you Ben.