Assertion

Two types of assertions: Immediate assertion and Concurrent assertion
When to use which and why?
Where to use which and why?

I found this in one book: “assertions help to increase productivity of the design/debug/simulate/cover loop.” My question is “HOW?”.

In reply to Mittal Maru:

Two types of assertions: Immediate assertion and Concurrent assertion
When to use which and why?
Where to use which and why?

What is your understanding of these 2 types of assertions?
What are your issues or concerns?
Provide examples.
Once you do that, I can help in your understandings.
Ben systemverilog.us

What is your understanding of these 2 types of assertions?
What are your issues or concerns?
Provide examples.
Once you do that, I can help in your understandings.

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my understanding is as below:
→ Immediate assertion asserts at clock tick.
→ Concurrent assertion asserts at every clock edge. It can be asserted by using property.
→ Difference between both is “property” keyword.

In reply to Mittal Maru:

my understanding is as below:
→ Immediate assertion asserts at clock tick.
→ Concurrent assertion asserts at every clock edge. It can be asserted by using property.
→ Difference between both is “property” keyword.

You need to take a look at either the IEEE Std 1800™-2017 section 16 on assertions or get a good book on SVA or free tutorial material online.
https://www.doulos.com/knowhow/sysverilog/tutorial/assertions/

https://www.win.tue.nl/~jschmalt/teaching/2IMF20/bsnug04_ecker_esen_kruse_steininger_jensen.pdf

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr


  1. SVA Alternative for Complex Assertions
    https://verificationacademy.com/news/verification-horizons-march-2018-issue
  2. SVA: Package for dynamic and range delays and repeats - SystemVerilog - Verification Academy
  3. SVA in a UVM Class-based Environment
    https://verificationacademy.com/verification-horizons/february-2013-volume-9-issue-1/SVA-in-a-UVM-Class-based-Environment