Assertion

SystemVerilog
1

write an assertion which will test that when clockgate variable goes low we have to capture time and then we need to check whether variable a && b && c && d && e goes high and the time period and then check the difference of both time period is == clockgate_hysteresis value( which is programmed dynamically)

2

In reply to bhajanpreetsinght:

See https://verificationacademy.com/forums/systemverilog/assertion-test-3-signals-where-when-goes-high-it-should-b-or-c-go-high-and-checking-should-continue-till-high

3

In reply to ben@SystemVerilog.us:

Hi Ben,

I have a very tough requirement I need to capture time to illustrate wrong assertion
in the same solution which you gave suppose I need to check a&& b&&c && d&& e to be high at that capture time as start and similarly when w goes low for 2 consequitive clock capture end time and then the difference between them should be equal to - dynamic delay then assertion pass or fails.

4

In reply to bhajanpreetsinght:

i am finding extremely difficult to use $time to capture time as it throws erroe

5

In reply to bhajanpreetsinght:

  1. What are your requirements. Be clear about them. Try to make them in bullet points.
  2. Show code, and results. What are the issues.

I don’t mind answering questions, but I am not going to guess as to what you are really asking or what issues you see.

6

In reply to ben@SystemVerilog.us:

Hi ben,

First requirement is check all the five signal is high then capture the timestamp
2: second requirement is that when clockgated a variable goes low for 2 or more consecutive clock capture the timestamp
3: Requirement check the difference of both timestamp should be equal to a dynamic value variable clockgate_hystersis which is set at start can be any value as it is [11:0] variable

combining all three in need to write a assertion which checks false occurance of clockgate, as per the last discussion with you I got the correct occurance through this code

In reply to bhajanpreetsinght:

// Requirements should be defined by an implementation, and this is what I see.
// I am struggling with your requirements. This is what I understand:
// 1) a, b, c, d, e must remain hi for a duration defined by a variable.
// 2) At the end of this duration of cycles, signal w should reamin deasserted (i.e., w==0) for 1 to 3 cycles.
// [Ben] This test is to be done for any string of a, b, c, d, e that remains hi for that period of cycles.
// 3) If a, b, c, d, e do not remain hi for the dynamically specified duration,
// this is a don’t care situation.
//
//[Ben] This type of spec appears to be a sync pattern
/* I intend to use the dynamic repeat from the package
//----------------------------------------------------------------
// ****** DYNAMIC REPEAT q_s[*d1] **********
// Implements a_sequence[*count]
// Application: rose(a) |-> sq_rpt_simple_count(sq_1, d1) sequence sq_rpt_simple_count(sq, count); int v=count; (1, v=count) ##0 ( v>0 ##0 sq, v=v-1) [*1:] ##0 v<=0;
endsequence // sq_rpt_simple_count
//Note: “The sequence_expr of a sequential property shall not admit an empty match (see 16.12.22).”
*/

module m;
import sva_delay_repeat_range_pkg::*;
bit clk, a, b, c, d, e, w;
int duration;

sequence q_abcde; @(posedge clk) a && b && c && d && e; endsequence
assert property(@(posedge clk)
sq_rpt_simple_count(q_abcde,duration) |-> w==0[*1:3]);
endmodule

Which you gave ,now we got a big for that I nee to write an assertion on timestamp with my 3 requirements

7

In reply to ben@SystemVerilog.us:

In reply to bhajanpreetsinght:

  1. What are your requirements. Be clear about them. Try to make them in bullet points.
  2. Show code, and results. What are the issues.
    I don’t mind answering questions, but I am not going to guess as to what you are really asking or what issues you see.

so to conclude I need to write a code something

If a&& b&&c&&d&&e capture time1;
If clockgated is low for two consecutive clocks capture time2;

Third requirements: difference between time1:time 2 should be equal to clockgate_hysteresis value,if this happens pass if not fail

8

In reply to ben@SystemVerilog.us:

In reply to bhajanpreetsinght:

  1. What are your requirements. Be clear about them. Try to make them in bullet points.
  2. Show code, and results. What are the issues.
    I don’t mind answering questions, but I am not going to guess as to what you are really asking or what issues you see.

It is a very tough question in this one please answer

9

In reply to bhajanpreetsinght:

In reply to ben@SystemVerilog.us:
It is a very tough question in this one please answer

I tried using this code it fails in syntax

module YourModule (
    input logic a,
    input logic b,
    input logic c,
    input logic d,
    input logic e,
    input logic clockgate,
    input logic clk,
    output logic assertion_passed
);

    // Your module logic here

    logic [31:0] start_time;
    logic [31:0] end_time;
    logic capturing;

    // Property to capture start time when a && b && c && d && e are all high
    property prop_capture_start_time;
        @(posedge clk) (a && b && c && d && e);
        start_time <= $time;
    endproperty

    // Property to capture end time when clockgate goes low for two consecutive clocks
    property prop_capture_end_time;
        @(posedge clk) (clockgate == 1'b0)[*2];// fails here [*2, stating syntax error
        end_time <= $time;//it fails here
    endproperty

    // Property to check the time difference and capturing state
    property prop_check_time_difference;
        @(posedge clk) (start_time != 0) ##1 (end_time != 0) |-> (end_time - start_time == clockgate_hysteresis);
    endproperty

    // Apply the assertion using the properties
    assert property (
        prop_capture_start_time |-> (prop_capture_end_time ##1 prop_check_time_difference)
    )
    else begin
        assertion_passed <= 0;
        $error("Assertion failed!");
    end

endmodule

so tried using always(@posedge clk)
begin
if(a && b && c && d && e)
$display(" start_time= %d",$time);
similarly if (clocgated ==0[*2])// it shows syntax erroe

10

In reply to bhajanpreetsinght:

// First requirement is check all the five signal is high then capture the timestamp
// 2: second requirement is that when clockgated a variable goes low for 2 or more consecutive clock
// capture the timestamp
// 3: Requirement check the difference of both timestamp should be equal to a dynamic value
// variable clockgate_hystersis which is set at start can be any value as it is [11:0] variable
// combining all three in need to write a assertion which checks false occurance of clockgate,
// as per the last discussion with you I got the correct occurance through this code

  1. Just labeling something as a “requirement” does not make it a “requirement”
  2. What you wrote is not a set of requirements about what functions are needed to be tested.
    What you wrote, along with the code, is more of an implementation of how to test.
  3. A requirement would be something like: When input XX sensors are activated then
    within xx ns, determined by a parameter, the control xxx shall be bla-bla-bla…a
  4. A test plan may say something like: SVA assertions with simulation (and not formal)
    shall be used along with constrained random tests. The assertions used shall be independent
    of the implementation and be derived from the requirement specification defined in …
    Tests to be performed shall include the ensors …
  5. BTW, I also don’t know where hysteresis comes in. :
    Electronic Hysteresis: In electronics, hysteresis is often intentionally introduced into circuits using devices like Schmitt triggers. These circuits have two threshold voltages (one for rising input and one for falling input), which results in a “hysteresis loop” in the input-output relationship. This helps eliminate noise or unwanted oscillations in digital signals.
  6. You need to study SVA. There are several concepts that You need to understand,
    including attempts, threads, and local variables.
  7. Below is an attempt at coding what you wrote. I have doubts as to what you need as your understanding of the requirements and what needs to be tested are not clear.
    Again, STUDY SVA.

module YourModule (
    input logic a,
    input logic b,
    input logic c,
    input logic d,
    input logic e,
    input logic clockgate,
    input logic clk,
    output logic assertion_passed
  );
   
  
  realtime clockgate_hysteresis=2ns; 

 
  // From your code, it looks like you are trying to write something like:
  //  (a && b && c && d && e) |-> (clockgate == 1'b0)[*2] ##1 time_diff==value
  property check; 
  logic [31:0] start_time;
  logic [31:0] end_time;
    @(posedge clk) ( (a && b && c && d && e),  start_time = $realtime) |-> 
    (clockgate == 1'b0)[*2] ##0 (1, end_time = $time) ##0 
    (end_time - start_time == clockgate_hysteresis);
  endproperty

  ap_check: assert property(check); 
  // THE TIME MEASUREMENT IN THIS ASSERTION IS SORT OF MEANINGLESS AS 
  // by definition, (end_time - start_time) == 2 clock periods. 
endmodule

Best wishes,

Ben Cohen
Ben@systemverilog.us
Link to the list of papers and books that I wrote, many are now donated.

or Links_to_papers_books - Google Docs

Getting started with verification with SystemVerilog

11

In reply to ben@SystemVerilog.us:

Here clkgate hysteresis is any dynamic value set we cannot set to 2ns