in below assertion for clock domain crossing what does the ##1 delay is equal to? is it equal to one clock cycle of src_clk or timescale defined in environment.I have same doubt for other ##1 present in code. When third time ##1 is given then how much delay will it be?
one clock cycle of your clock; in fact concurrent assertions are always based on a clock:
16.2 LRM:
Concurrent assertions are based on clock semantics and use sampled values of their expressions
16.5 Concurrent assertions overview
Concurrent assertions describe behavior that spans over time. Unlike immediate assertions, the evaluation
model is based on a clock so that a concurrent assertion is evaluated only at the occurrence of a clock tick.
It has to have a clock somewhere; either you explicitly describe it as you have done, or it will implicitly pull it from a default clocking block (if you have one)
when i write ##1 for the third time , does it mean tick of dst_clk or src_clk or clock of default clocking block ?
what if i write below code, then does the third ##1 corresponds to default clock or tick of src_rdy?
assert property ( @(posedge src_rdy) rose(strobe) |-> (
strobe[*1:] ##1 1 )
) intersect (
##1 @(posedge dst_rdy) strobe[*3]
##1 @(posedge src_rdy) 1
)