Assertion

SystemVerilog
,
1

Hi All,

I am verifying a serial protocol where timings of protocol is very important.

I would like to do protocol checks using assertion. In assertions, i would like to do time check and code looks as below.

`define tHD_STA 25us
//Checking start condition and checking the hold time (tHD:STA)
assert property start_bit_hold_chk;
else
$fatal(0,“Hold time violation after start bit”,$time);

property start_bit_hold_chk;
$fell(smb_data) |-> (smb_clk && #`tHD_STA $fell(smb_clk));
endproperty

As per my knowledge we cann’t specify exact delay in assertions.

How do i put exact delay in assertion?
Do let me know if any other method is available to specify delay.

2

Try creating a multi-clocked sequence. In this case create a delayed clock, of the mentioned delay, and use it in a multi-clock assertion.

always @ (sta_clk) begin #25 sta_clk <= smb_clk; end 

property start_bit_hold_chk;
$fell(smb_data) |-> (smb_clk ##0 @(posedge sta_clk) $fell(smb_clk));
endproperty