Assert naming in procedural code

SystemVerilog
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1

Hi,

is it possible to make assert naming generic within a procedural code?

let’s take the following example:


  task check_flag(bit flg, bit value);
     //...
     name :assert(flg == value);
     //...
    end 
  endtask : check_flag

the above routine is called in several places each time with a different flag, how can I make “name” generic depending on flag name during routine call?

Thanks,

2

In reply to Mohamed_TN:

There is no way to dynamically name immediate assertions, nor is there a way to find out the name of a variable passed to a task.

If you are trying to do this to collect coverage information, you could pass the name of the flag as another argument to the task and use a covergroup instead or in addition to the assertion. Each call to the task would create a new covergroup instance that can be given a unique name.

Another option is wrapping the check_flag task as a static method of a parameterized class. You would parametrize the class with the string name of the flag for each call you need to make. Each parameterization of the class creates a new specialization of the class type which would give you a unique name for your assertion.

3

In reply to dave_59:

It is for coverage information purpose,
Thanks a lot Dave,