Asserions to count the number of clock cycles

[sid1406]

Hi all,

I wanted to know whether we can use assertions to count the number of clock cycles. I have a signal A which goes high at any time and after certain time it will go low. But when the signal is high, it triggers another clock signal and the clock signal gets cut off as soon as the signal A goes low. Now i want to find out how many clock cycles are there until the signal A is high.

Is there a way to use assertions to find that out.

Please advice.

Thanks,
Sid

[ben2]

In reply to sid1406:

An assertion is a statement that a design property is correct; it does not have to be expressed in SVA, it could be straight SystemVerilog. Your requirements are best handled with SystemVerilog. See Paper: VF Horizons:PAPER: SVA Alternative for Complex Assertions | Verification Academy

Ben Cohen
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See Paper: VF Horizons:PAPER: SVA Alternative for Complex Assertions | Verification Academy