Here is a simple transaction item I coded as below.
class my_trans extends uvm_sequence_item;
function new(string name = "my_trans");
super.new(name);
endfunction : new
rand logic [7:0 ] id;
rand logic [47:0] info;
constraint my_cons {
id >= 8'h1;
id <= 8'h9;
}
The first constraint I want to use is the id could only be selected from 1 to 9. (just like what I coded …)
but another constraint I have no idea how to program is: The id in the current transaction can not be the same as the one in previous transaction. For example, if the id is randomized to 3 in this transaction to send (start_item/finish_item), and then the next id can’t be 3 again.
I tried your suggestion but failed at below syntax error.
Error-[SE] Syntax error
Following verilog source has syntax error :
“/proj/tb/my_seq.svh”,
20: token is ‘const’
id != const’(id);
^
SystemVerilog keyword ‘const’ is not expected to be used in this context.
one quick solution can be(though not very efficient):: just after randomization you can store each 8bit wide randomized value of id and check if current value is generated before or not. if yes than re-randomize the class.