Array of system verilog events

SystemVerilog
1

Hi

I am trying to use array of events to capture clocking when corresponding enable is asserted. I am seeing 2 issues:

  1. When the enable for one is de-asserted other events are not being triggered even if their enable is asserted.
  2. I am not able to plot the events from the array in the waveform. I am able to plot event not declared as an array.

Below is my implementation:

module event_array;
    event arr_event[int];

    function automatic event new_event();
       event e;
       return e;
    endfunction

    initial begin
       for(int i = 0; i < MAX; i++) begin
           arr_event[i] = new_event();
       end
    end
    
    generate
       for(genvar i = 0; i<MAX; i++) begin
          always @(posedge clk[i]) begin
              ->arr_event[i]
          end
       end
    endgenerate

endmodule

Can you please help me to understand the issue with this implementation.

2

In reply to Sudarshan:

You need to clarify what you mean be “enable”," “asserted”, and “de-asserted”. Are you talking about the clock itself, or an enable on the clock? Please show a complete runnable example.

There is no need for the function new_event(), unless there is more to the code than what you have shown.

We cannot provide tool specific help on this forum. You’ll need to read your tool vendors manual, or contact them for more help.