Array of constraints

SystemVerilog
1

Hi There,

In systemverilog is array of constraints possible?

i.e.

constraint cc[0] … ;
constraint cc[1] … ;

What I want to do is, I have a member called pkt_length 32 bits.

In a single simulation I run multiple packets.

For a given simulation I want pkt_length to be always 1, in another simulation the pkt_length to be always 2, in another simulation the pkt_length to be always [125:10000] and like that.

So I wanted to define array of constraints and enable constraint mode for only 1 of the constraint.

Thanks,
Sunil.

2

In reply to KumarSunilB:

No, there are no arrays of constraints. But there is a simpler approach to what you want.

Simply set two “knobs” at the beginning of your test, a min_pkt_length and max_pkt_length.

Then have the constraint

constraint cc{ pkt_length inside {[min_pkt_length:max_pkt_length]};}
3

In reply to dave_59:

Alright! Thank you.