Arranging/Including classes in multiple files

SystemVerilog
1

I am trying to simulate a testbench for a D Flip Flop verification. I have arranged my code in different files such monitor.sv, generator.sv, scoreboard.sv, driver.sv, transaction.sv, environment.sv and testbench.sv. I am including all the class files in a package.sv file and subsequently including this package in each of the class files. This is not working out for me since I get a simulation error. Is there a standard way to divide the classes and multiple files and include them.

Thanks.

2

In reply to totochan1985:

It would really help to show some code and especially the error message you are getting.

Also you import a package, not include it. See SystemVerilog Coding Guidelines: Package import versus `include - Verification Horizons

3

In reply to dave_59:

In reply to totochan1985:
It would really help to show some code and especially the error message you are getting.
Also you import a package, ni include it. See https://blogs.sw.siemens.com/verificationhorizons/2010/07/13/package-import-versus-include/

Above is the code. It works on the playground but when I try to compile it on Questasim, it throws errors such as “transaction definition not found”.

4

In reply to totochan1985:

You never include the package.sv file or import the package. Do not include the environment.sv file

5

In reply to dave_59:

In reply to totochan1985:
You never include the package.sv file or import the package. Do not include the environment.sv file

I have updated the code so you should see the package.sv file along with other changes. If I cannot `include or import the package, how do I use the package in my individual class files, environment and the testbench top to compile successfully?

6

In reply to totochan1985:

Make sure your files only get compiled once

EDAPlayground compiles your code with the command line

compile testbench.sv desgin.sv

If you want any other files compiled, you need to `include them in one of those two files, or know how and where to add them to the command line.

Please read the link SystemVerilog Coding Guidelines: Package import versus `include - Verification Horizons

Then look at your corrected code