Arithmetic expressions with unsigned and signed types

SystemVerilog
,
1

Hi all ,



module LRM_11_4_3_1;
  
  
 integer intS;
var logic [15:0] U;


initial begin

intS = -4'd12;
$display("%b , %d",intS,intS);
U = intS/3;
$display("%b , %d",U,U);


end 
  

endmodule  

I get Output as ::

11111111111111111111111111110100 ,  -12
1111111111111100 , 65532

I have a few Queries
[Q1] Within intS how am i Getting all MSB’s as 1’s . -4’d12 is ( 0100 ) , after sign extension shouldn’t it be { 28{1’b0} , 4’b0100 } ?
[Q2} During the division Operation would the Numerator be treated as signed or Unsigned ?
[Q3] How does U get its Value ?

Regards,

AGIS

2

In reply to Etrx91:

This is all explained in sections 11.6 thru 11.8 of the 1800-2017 LRM. Your statement is

( intS = - (4'd12))

Since this is a context-determined assignment operation, the operands on the RHS get sized to the LHS, then the unary negation operation gets applied.

Both numerator and denominator are signed. The result is -4.