Are there any way to use assertion for checking signal order?

SystemVerilog
1

hi all,

have you met this problem?

example:
(1) signals: s1, s2, s3, and s4
(2) signal asserted order s1->s2->s3->s4->s1… (rising edge order)
(3) s1 to s2, s2 to s3, s3 to s4, and s4 to s1 delays are all not fixed latency. (may be long latency)

Are there any SVA command can be used to ensure their order?

2

Yes, you can use SVA for signal ordering. For example : b ##[1:$]a specifies a sequence where ‘a’ signal at some point after ‘b’ signal has been asserted.