Are Nested Interfaces a thing?

SystemVerilog
1

I want to do something like:

interface frame_mon_intf(input clk);
    logic valid;
    logic data;
endinterface : frame_mon_intf

interface frame_mon_vif(input clk);
    frame_mon_intf sync_out0(clk);
    frame_mon_intf buf_out0(clk);
endinterface : frame_mon_vif

Is this legal? Right now I’m using Xilinx IDE and although it compiles, at runtime when I try to access the clock in my testbench i get an unhelpful fatal error message. I Want to make sure this is a legal thing to do in general before I file any tool bug with xilinx.

2

In reply to silverace99:

I nest interfaces. My simulator doesn’t seem to mind; I passed them in the port list, though.