Are code 1 and 2 same in system Verilog?

SystemVerilog
1

Code 1:

for (int i =0; i<3; i=i+1) begin
     automatic int k = i;
     fork
       $display(k);
     join_none
end

Code 2:

for (int i =0; i<3; i=i+1) begin
     fork
       automatic int k = i;
       $display(k);
     join_none
end
2

In reply to SanjanaDhiran:

You already asked, and I answered here: fork join_none inside for loop | Verification Academy