I have a design with different components that use the same protocol for communicating data between them. In my testbench, I need to use the same procedure to wait for data to become available at the output of each component and then collect and compare it to the expected results. I have coded those procedures in a system verilog task, and I have a task for each of the components in the system. The only difference between my tasks are the signals that are being tested.
I don’t like copying and pasting large blocks of code that are exactly the same except the signals being used. Is there a way in system verilog to reuse task code and somehow pass in those signals? Maybe a parameterized class? What is the best way to do this?
How about if you create a single interface with generic connections and then connect them to the required DUT pins at the testbench level? You can put your task inside the interface and use it as required.