Is another struct means another scope?

SystemVerilog
1

Can I write on SystemVerilog two structs in one module and then make enum in each struct with same literal (“IDLE” for example)? Is another struct means another scope?

Must it work or not?

`timescale 1 ns/ 1 ns
module test013_LITERAL (
    input  A,
    input  B,
    output C
);
    struct{enum{IDLE,
                SOME_STAGE_1} FSM;
             logic some_register;
            } first_machine;
    struct{enum{IDLE,
                SOME_STAGE_2} FSM;
             logic some_register;
            } second_machine;            
    assign C = A ^ B;    
endmodule
2

In reply to Arseniy Antonyuk:

This most likely does not work. The problem here is that both the struct and enum variables are being declared as anonymous types. The LRM is not very clear what the scope would be for these anonymous types inside the struct. But even if this syntax was allowed, there is no way to access “IDLE” as a bare identifier, as it would be ambiguous which enum label you were referring to,