Always_ff event controls

SystemVerilog
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1

Hello Guys

I need to get the below event control clarification in always_ff.

Statement1–> always_ff @(posedge clk, negedge rst) // this works fine

Statement2–> always_ff @(posedge clk or negedge rst) // same as above

Statement3–> always_ff @(posedge (clk || rst ))
Statement4–> always_ff @(posedge clk || rst) // both the statements executes

Statement5–> always_ff @(posedge clk || negedge rst) //is a syntax error

Question 1 :
Can someone please explain the difference between above 5 statements and why the statemnet5 is an error, is it just a syntax error or some logical error.

Question 2 :
LRM of SV says, “The always_ff procedure imposes the restriction that it contains one and only one event control and no blocking timing controls.”

Then how does it is a single event control for statement 1 and 2 which is getting evaluated on both posedge clk and negedge rst??

Question 3 :
If all the above statements are single event controls, when @ is considered for event trigger, can always block have more than 1 event controls, if so how??

Thanks
Manjush

2

In reply to manjush_pv:

See section 9.4.2 Event Controls Statement 5 is an error because you can’t perform any logical or arithmetic operation on an event expression. Statements 3 and 4 are creating event expressions from the result of logical expression (clk || rat). It the same as if you had written

assign temp = clk || rest;
always_ff @(posedge temp)

An event control is @(event_expression). As long as there is one ‘@’ then that is valid for always_ff, Synthesis coding rules require that the synchronous and asynchronous be listed in the single event control.

Most synthesis tool do not allow more than one event control in any always block, but higher level synthesis tool, and any code you write that will not be synthesized can have more than one event control

always begin
     @(posedge clk)
        state = s1;
     @(posedge clk)
       state = s2;
     end
3

In reply to dave_59:

Thank you Dave!!!