In reply to dave_59:
There is an implicit always associated with concurrent assertions, thus allowing the assertion to be retested at each occurrence of its clocking event. For example:
initial
ap_resetf_hi_ater_hi: assert property(@ (posedge clk)
##20 |=> always reset_f==1'b1 );
Note that assertion ap_resetf_hi_ater_hi is attempted ONCE because of the initial.
However, after 20 cycles, reset_f must always stay in the high state.
You could write this as
initial begin
repeat(20) @(posedge clk);
forever
always @(posedge clk)
ap_reset_f_hi: assert property(reset_f==1'b1 );
end
Ben Cohen
http://www.systemverilog.us/
For training, consulting, services: contact
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*
SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
* A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
* Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
*
Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
* Component Design by Example ", 2001 ISBN 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
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