Can somebody explain the difference between these two code blocks?
1st block:
@always(posedge clock) begin
b = c;
a = d;
e <= f;
g <= h;
end
2nd block:
begin
b = c;
a = d;
e <= f;
g <= h;
@always(posedge clock) end
Will the two blocks behave differently? If not in this case, is there any other case you can explain where they behave differently.
Thanks.
In reply to likhith bommu:
Both code blocks or not legal syntax. Please show complete examples to make sure the know the context of the question.
See Asking better questions on the Verification Academy Forums with EDAPlayground - Verification Horizons
Hi Dave,
Sorry for not providing complete code. I tried to create 2 modules. Hope this will help you to understand my question.
module scene_one (input clock,input a, input b, input c, input d, output reg o, output reg o_d);
always @ (posedge clock) begin
o = ~((a & b) | (c^d));
o_d <= o;
end
endmodule
module scene_two (input clock,input a, input b, input c, input d, output reg o, output reg o_d);
begin
o = ~((a & b) | (c^d));
o_d <= o;
always @ (posedge clock);
end
endmodule
Can you explain how each module samples the data and provides the output?