@always position

Question

Can somebody explain the difference between these two code blocks?

1st block:

@always(posedge clock) begin
b = c;
a = d;
e <= f;
g <= h;

end

2nd block:

begin
b = c;
a = d;
e <= f;
g <= h;
@always(posedge clock) end

Will the two blocks behave differently? If not in this case, is there any other case you can explain where they behave differently.

Thanks.

Answer 1

dave_59

Forum Moderator

10091 posts

January 12, 2021 at 11:55 am

In reply to likhith bommu:

Both code blocks or not legal syntax. Please show complete examples to make sure the know the context of the question.

See https://blogs.sw.siemens.com/verificationhorizons/2020/04/29/forums-with-edaplayground/

— Dave Rich, Verification Architect, Siemens EDA

Answer 2

likhith bommu

Forum Access

5 posts

January 16, 2021 at 7:06 am

Hi Dave,

Sorry for not providing complete code. I tried to create 2 modules. Hope this will help you to understand my question.

module scene_one (input clock,input a, input b, input c, input d, output reg o, output reg o_d);
always @ (posedge clock) begin
o = ~((a & b) | (c^d));
o_d <= o;
end
endmodule

module scene_two (input clock,input a, input b, input c, input d, output reg o, output reg o_d);
begin
o = ~((a & b) | (c^d));
o_d <= o;
always @ (posedge clock);
end
endmodule

Can you explain how each module samples the data and provides the output?

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