Alternative for disable_iff (rst_n==0) in assert proprty

SystemVerilog
, , , , ,
1

Hi all,

I’m using the latest 2016 VCS version and see an issue where disable iff cannot be used in an assertion property.

 property valid_check;
      @(posedge clk)
	disable iff (!rst_n) (re[i] |=> valid[i-1]);
 endproperty

I see this error:

Lint-[SVA-DIU] Disable iff used
Disable iff is used in assertion 'genblk10Û0Ý®unnamed$$_0: assert
property(@(posedge clk) disable iff ((!rst_n)

Is there an alternative for disable_iff?

2

In reply to tejaswig:
This forum does not discuss tools. However, looking at 1800, your code is correct.


property_declaration ::=
  property property_identifier [ ( [ property_port_list ] ) ] ;
   { assertion_variable_declaration }
   property_statement_spec
endproperty [ : property_identifier ]

property_statement_spec ::=
  [ clocking_event ]
  [ disable iff ( expression_or_dist ) ]
  property_statement

Thus, the following code looks OK:


module top; 
	bit clk, rst_n=1;  
  logic[15:0] i, valid, re; 
	default clocking @(posedge clk); endclocking
	initial forever #10 clk=!clk;   
property valid_check;
      @(posedge clk)
	disable iff (!rst_n) (re[i] |=> valid[i-1]);
 endproperty
  ap: assert property(valid_check);  
  
endmodule

I suggest that you contact your tool vendor support.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us

  • SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
  • A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
  • Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
  • Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
  • Component Design by Example ", 2001 ISBN 0-9705394-0-1
  • VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
  • VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
3

In reply to ben@SystemVerilog.us:

thanks for your response!

4

In reply to tejaswig:

That looks like a Lint message, look for it in your VCS doc. Maybe there is a reason why they discourage it? Perhaps because disable iff can’t be nested and hence could better be used with assert than property. I would also recommend to use “default disable iff”.

Regards
Srini
www.verifworks.com