Forums: SystemVerilog
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enmixing signed and unsigned numbers in sv/v
https://verificationacademy.com/forums/systemverilog/mixing-signed-and-unsigned-numbers-sv/v
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<p>Hello </p>
<p>In below code<br />
check1 comes out FFFF_FFF5<br />
check2 comes out 3FFF_FFF5<br />
check3 comes out b<br />
I understand that when I do -44/4, -44 is expressed in 2s complement form and we divide by 4 to get answer -11 which is expressed in 2s complement form.<br />
However in check2, my understanding is anything in base format is considered unsigned. So 6'o54 would be positive 44 in 2s complement. this would be divided by 5 to get 11. with negative sign in front, it would again take 2s complement (its like 0 - 11), so answer should be same as check1 but its different.</p> </div>
Fri, 20 Jan 2023 21:57:22 +0000aashishs2603110591 at https://verificationacademy.comSystemVerilog Constraint Help for Negative/Postiive numbers
https://verificationacademy.com/forums/systemverilog/systemverilog-constraint-help-negative/postiive-numbers
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<p>Hi,</p>
<p>I have three values which are signed logic vectors as shown below. I am trying to build a constraint where the sum of the three numbers, positive and negative included should be less than a constant.</p>
<p>parameter signed LIMIT = 200;<br />
rand logic signed [15:0] a;<br />
rand logic signed [15:0] b;<br />
rand logic signed [15:0] c;</p>
<p>constraint limit {a+b+c < LIMIT);</p>
<p>I tried the above code snippet but it does not obey the constraint.I would like the value of a ,b and c be negative/and or positive but the sum to be less than the constant.</p> </div>
Fri, 09 Oct 2020 01:38:04 +0000kk911093910 at https://verificationacademy.com