Aliasing

Please explain in simple words with a example that what is signal aliasing in system verilog and why do we use it? Is it has any importance in verification?

In reply to SidRaj:

Please explain in simple words with a example that what is signal aliasing in system verilog and why do we use it? Is it has any importance in verification?

None whatsoever. The let statement is much more powerful.

In reply to dave_59:

Sorry I couldn’t understand what you want to say

In reply to SidRaj:
I saying it has no importance. One less feature to remember.