Alias In systemverilog

SystemVerilog
,
1

the System Verilog ‘alias’ keyword. This is similar to continuous assignment, but it is bi-directional, so useful with inouts
below is the example to alias keyword.
module swap (
inout wire [31:0] a,
inout wire [31:0] b);

alias {a[7:0],a[15:8],a[23:16],a[31:24]} = b;

endmodule
how can implement the testbench code for above code? and in testbench which data type will take for inout nets?

2

In reply to anvesh dangeti:

Only nets (
wire) signals can be connected to inout ports. See my DVCon paper and the section on bidirectional ports.