Adding multiple values in a associative array

SystemVerilog
1

I have been trying to create an associative array in the following format,
page = {0x40000000:{0x10000401,0x10000501,0x10000601}, 0x40001000:{0x10000801,0x10001801,0x10000C01}}
here both the key and values are 64bit hexdecimal values.

this is what i have written,

bit[63:0] page[bit[63:0]][bit[63:0]];
base_addr='h40000*'h1000;
pte='h10000401;
page[base_addr]=pte;      //I get an error over here, incompatible complex type assignment

Is my syntax, assignment right? any idea why I an facing this error ?

Thank you

2

In reply to bharath2k1:

Perhaps you meant

bit[63:0] page[bit[63:0]]

and did not mean to declare a 2-dimensional associative array

3

In reply to dave_59:

I wanted a two dimensional array itself, I figured that my assignment syntax was wrong. That was the error. Thank you